# Putting a CPU Inside Qwen: How Qwenputer Runs RISC-V Within the Model


![](https://leafw-blog-pic.oss-cn-hangzhou.aliyuncs.com/qwenputer-cover.png)

On October 22, a researcher named Divyansh Agrawal published a fascinating technical write-up: [Qwenputer: a fully functioning, deterministic RISC-V CPU inside Qwen3.5](https://divagr.com/blog/qwenputer).

The author did something that sounds almost impossible: **embedded a complete 32-bit RISC-V CPU inside the neural network of Qwen3.5-4B.**

This CPU can execute integer arithmetic and C programs, and its underlying compute core can even run MicroPython. It doesn't call an external Python interpreter or any calculation tool; the CPU instructions themselves are executed by the model's forward pass.

Even more interesting, the CPU requires no training at all. The author used a compiler to construct the network weights directly, compiling registers, an arithmetic logic unit, and instruction control circuitry into the Transformer.

The original Qwen3.5-4B can still chat, answer questions, and reason as usual. The newly added CPU handles tasks that require exact computation.

The project is open source:

- [Original write-up](https://divagr.com/blog/qwenputer)
- [GitHub: Qwenputer](https://github.com/divagr18/qwenputer)
- [Hugging Face model](https://huggingface.co/divagr1925/Qwen3.5-4B-Qwenputer)

Three things in this work deserve the most attention: how Gated DeltaNet is turned into genuinely addressable RAM, how CPU circuitry is compiled into model weights, and how the token generation process is used to drive CPU execution.

## 1. How Can There Be a CPU Inside a Large Model?

First, a concept that is easy to misunderstand.

The large models we use every day are, at bottom, software running on hardware such as CPUs and GPUs. A model's parameters are sets of numbers, and the forward pass is a sequence of mathematical operations: matrix multiplications, additions, and nonlinear activations.

When Qwenputer talks about "embedding a CPU in the model," it does not mean fabricating a new physical chip inside the GPU.

Instead, it uses the network's mathematical operations to build a computing circuit that follows RISC-V instruction semantics.

The word CPU actually has two meanings.

At the hardware level, a CPU is a physical chip made of transistors, logic gates, registers, and so on. At the computational level, a CPU is a system that can fetch instructions, perform operations, read and write memory, and control the flow of program execution.

The second meaning can be implemented entirely in software.

For example, we could write a very simple CPU emulator in Java:

```java
public class VirtualCPU {
    int[] registers = new int[32];
    byte[] memory = new byte[1024];

    void add(int rd, int rs1, int rs2) {
        registers[rd] = registers[rs1] + registers[rs2];
    }
}
```

Keep adding instruction decoding, conditional branches, memory addressing, and so on, and you gradually end up with a RISC-V emulator.

What makes Qwenputer special is that it converts this computational logic into neural network operations.

Take the RISC-V instruction:

```asm
ADD x3, x1, x2
```

It means: read the values in registers x1 and x2, add them, and write the result to x3.

A real CPU executes this instruction with physical logic circuits, a Java emulator executes it with integer arithmetic in a program, and Qwenputer performs the read, the addition, and the write-back with specially designed neural network layers.

So we can think of Qwenputer as: **a deterministic computing system implemented in neural network weights, added inside a large model responsible for language understanding and reasoning.**

This is clearly different from traditional LLM tool calling.

![Comparison of a traditional LLM calling external tools versus Qwenputer's built-in RISC-V CPU](https://leafw-blog-pic.oss-cn-hangzhou.aliyuncs.com/qwenputer-llm-tools-vs-internal-cpu.png)

For example, ask the model to compute:

```text
123456789 × 987654321
```

A regular Qwen can work it out step by step using its language-model abilities, or it can call an external calculator.

Qwenputer, by contrast, can perform deterministic integer arithmetic with the RISC-V CPU inside the model and arrive at:

```text
121932631112635269
```

An important distinction: Qwen is still responsible for deciding when a calculation is needed and what to calculate. The CPU only executes operations according to explicit instruction rules.

**This means a probabilistic language model and a deterministic computing circuit can coexist in the same set of model weights.**

## 2. The Key Breakthrough: Turning Gated DeltaNet into Real RAM

This is the core of understanding Qwenputer, and in my view the most technically valuable part.

### 1. What Is Gated DeltaNet Originally For?

The standard Transformer we know uses the attention mechanism to process context.

During autoregressive inference, the model usually stores the Keys and Values of past tokens, known as the KV cache.

As the context grows longer, the KV cache that must be stored grows larger and larger.

Gated DeltaNet takes a different approach.

It is a linear recurrent network with a gated update mechanism. Each head maintains a fixed-size state matrix that is continuously updated as tokens come in.

![Standard attention's per-token growing KV cache versus Gated DeltaNet's fixed-size state matrix](https://leafw-blog-pic.oss-cn-hangzhou.aliyuncs.com/qwenputer-attention-vs-gated-deltanet.png)

The most intuitive differences between the two:

- The standard KV cache grows as the number of past tokens increases.
- Gated DeltaNet's recurrent state matrix has a fixed size; each token updates the existing state.

Qwen3-Next and Qwen3.5 use a hybrid attention architecture in which roughly three quarters of the attention layers use Gated DeltaNet.

Normally, these state matrices hold continuous vector information learned by the model and cannot be read or written precisely by address the way computer RAM can.

The author found that with some special settings, Gated DeltaNet can be made to behave like RAM.

### 2. How Are Exact Memory Reads and Writes Achieved?

The Gated DeltaNet state update can be expressed with a simplified formula:

$$
S_t = \alpha_t S_{t-1} + \beta_t k_t(v_t^\top - k_t^\top S_{t-1})
$$

Where:

- $S$: the state matrix, which can be thought of as memory.
- $\alpha$: the forget gate, which determines how much old data is retained.
- $\beta$: the write strength.
- $k$: the vector used to select the write location.
- $v$: the data to be written.

The author fixes two key parameters:

$$
\alpha=1,\qquad \beta=1
$$

and then sets the Key to a one-hot vector.

A one-hot vector is very simple, for example:

```text
[0, 1, 0, 0]
```

Only the second position of this vector is 1; all others are 0.

When used as an addressing vector, it selects only the second row of the state matrix.

Suppose we have this block of memory:

| Memory address | Before write | After write |
|---|---:|---:|
| 0x00 | 10 | 10 |
| **0x01** | **20** | **99** |
| 0x02 | 30 | 30 |
| 0x03 | 40 | 40 |

When the one-hot Key points to address 0x01 and the value 99 is written, only the data at that position changes.

Because $\alpha=1$, the old data at all other positions is fully preserved.

Because $\beta=1$, the new data directly overwrites the old data at the target position.

To read, use the same one-hot Query and you get back the value stored at that position.

In this way, a state matrix originally used to hold the model's contextual information gains capabilities like the following:

```java
memory[address] = value;   // WRITE

value = memory[address];   // READ
```

The real implementation also involves head allocation, address encoding, and numerical precision control, but this is the core principle.

More importantly, **this RAM does not need ever-growing storage as the context length increases.**

Using multiple Gated DeltaNet heads, the author built the state storage the CPU needs: RAM, registers, the program counter, and so on.

The key significance of this work is showing that the recurrent state inside a neural network can be constructed into a reliable, addressable storage device.

Of course, this capability comes from specially constructed weights and controlled numerical representations. The Gated DeltaNet in a regular Qwen3.5 does not natively support such exact reads and writes.

## 3. The Second Breakthrough: CPU Circuitry Can Be Compiled Directly into Model Weights

With RAM in place, the next step is building the CPU.

A traditional CPU consists of components such as registers, an ALU, and a control unit.

Executing an instruction requires a series of operations, such as reading registers, performing arithmetic, writing back results, and updating the program counter.

The author's idea is to translate these hardware operations into mathematical operations that a neural network can express.

| Traditional CPU component | Qwenputer implementation |
|---|---|
| Registers | Gated DeltaNet state |
| RAM | Multiple Gated DeltaNet heads |
| ALU | MLP / SwiGLU circuits |
| Instruction decoding | Logic circuits in neural network layers |
| Program counter (PC) | Dedicated state storage |
| CPU clock advance | Token decoding process |

The actual implementation uses 11 newly added layers of compute circuitry, placed before the 32 layers of the original Qwen3.5-4B.

This CPU supports the RV32IM instruction set, the Zba extension, and an additional big-integer arithmetic unit.

The author's technical documentation also lists the relevant storage:

- RAM: 32 KB.
- Read-only data region DROM: 128 KB.
- Program ROM: 256 KB.

### Why Can an MLP Emulate a CPU?

Because the linear transformations and nonlinear activations in a neural network can be combined into deterministic logic functions.

For example, for two binary inputs $a,b$, properly designed network weights can implement logic such as AND, OR, and XOR.

Combining these further lets you build components such as adders, comparators, and shifters.

As long as these basic operations can be implemented, together with registers and instruction control, it becomes possible to assemble a complete CPU.

The author defines the CPU as a series of basic operations and hands them to a compiler:

![Pipeline compiling RISC-V CPU circuitry into neural network weights and merging them into Qwen3.5-4B](https://leafw-blog-pic.oss-cn-hangzhou.aliyuncs.com/qwenputer-cpu-compile-pipeline.png)

The most unusual point here: **the weights of the entire CPU are computed directly by the compiler, without any gradient-descent training.**

The original Qwen3.5-4B weights remain unchanged.

In other words, the model now contains capabilities from two different sources:

One comes from pretraining, where language understanding, knowledge, and reasoning are learned from large amounts of data.

The other comes from the compiler, where deterministic program execution is obtained by designing the weights directly.

This is why the work is described as *Compiled Weights*.

It shows that, beyond storing capabilities acquired through training, neural network weights can also carry computing circuits designed directly by humans.

## 4. The Third Key Design: Token Generation Is CPU Execution

The CPU is in the model, so how does it run?

The answer is through the model's autoregressive token decoding process.

The author designed a special token protocol so that each forward pass of the model advances CPU execution.

It includes three important kinds of tokens:

| Token | Purpose |
|---|---|
| `ADDR` | Specifies the memory location to write to |
| `VAL` | Provides the data to write |
| `STEP` | Marks the completion of one instruction execution step |

During execution, the CPU keeps generating these special tokens, forming an execution trace.

Each time the model generates a relevant token, the compute circuitry performs the corresponding operation and updates the state stored in Gated DeltaNet.

### How Does Qwen Know When to Call the CPU?

The author borrows the tool-calling format Qwen is already familiar with.

For example:

```text
用户：123456789 * 987654321 等于多少？

Qwen：
<tool_call>
calc("123456789 * 987654321")
</tool_call>
```

(The user asks: "What is 123456789 * 987654321?")

With ordinary tool calling, an external program has to parse the call generated by the model and then launch Python or another calculation tool.

In Qwenputer, the compute circuitry receives this call, performs the calculation, and the tool response is then generated inside the model.

The overall process looks roughly like this:

![Sequence diagram of Qwen3.5 calling the embedded RISC-V CPU and DeltaNet RAM to complete a calculation after a user question](https://leafw-blog-pic.oss-cn-hangzhou.aliyuncs.com/qwenputer-calc-sequence.png)

So from the outside, Qwenputer appears to be calling an ordinary calculator tool.

But in reality, the computation happens in the neural network compute layers inside the model.

To load firmware and manage execution state, the current implementation also uses a lightweight driver called `RvChat`. It initializes memory and keeps the CPU's execution trace from interfering with the original Qwen's normal language reasoning.

So the current version still needs a dedicated runtime driver and cannot yet complete the whole execution process through the standard `generate()`.

### Is CPU Computation Fast?

Quite the opposite.

Because every CPU instruction has to go through the model's token decoding process, execution is far less efficient than on a real CPU.

With an optimized Triton executor, the author achieved roughly 3,200 CPU trace tokens/s on an NVIDIA L4 GPU.

That number doesn't look low, but keep in mind that a single CPU instruction may consume multiple tokens, and complex computations require executing a large number of instructions.

As a result, a complex calculation may take several seconds, whereas an ordinary CPU can usually finish it in milliseconds or less.

At this stage, the approach is not competitive in terms of compute performance.

## 5. How Well Does It Work?

The author first verified that the CPU itself runs correctly.

According to the published results:

- It passed the official RISC-V instruction tests.
- Test program outputs match QEMU.
- Free-running tests totaling about 18 million instructions found no errors.
- About 230,000 output positions controlled by the compute circuitry showed no mismatches against the reference implementation.

Free-running means the CPU keeps executing based on its own previous results, without a reference emulator correcting its state at each step.

This shows it is already capable of executing fairly long programs.

That said, these are results reported by the author and cannot be considered a formal proof of correctness for all inputs and execution environments.

### Accuracy on Math Tasks

Using the DeepMind arithmetic test set and the NUPA long-integer arithmetic benchmark, the author compared the original Qwen3.5-4B, Qwenputer, and Qwen3.5-4B equipped with an external Python tool.

![Accuracy of Qwenputer versus the original Qwen3.5-4B and an external Python tool on NUPA and DeepMind arithmetic tests](https://leafw-blog-pic.oss-cn-hangzhou.aliyuncs.com/qwenputer-benchmarks.png)

*Figure: Qwenputer accuracy comparison on arithmetic tasks. Source: Divyansh Agrawal, [original Qwenputer post](https://divagr.com/blog/qwenputer).*

The DeepMind results are as follows:

| Task | Original Qwen | Qwenputer | Python tool |
|---|---:|---:|---:|
| Large-integer multiplication | 55% | 97.5% | 100% |
| Large-integer division | 72.5% | 97.5% | 95% |
| Long mixed multiply/divide | 90% | 100% | 97.5% |
| Large-integer add/subtract | 87.5% | 97.5% | 97.5% |

*Each DeepMind task set contains 40 questions. Accuracy here is the accuracy of the whole model on the questions, not the CPU's instruction accuracy.*

As you can see, on these tasks Qwenputer already performs very close to Qwen with an external Python tool, and even slightly better on some tests.

On the NUPA long-integer arithmetic benchmark, accuracy rose from 48.6% for the original Qwen to 100%, matching the result with an external Python tool.

But there is a very important detail here.

**Even if the CPU itself computes correctly, the model as a whole cannot guarantee a correct answer to every question.**

That's because Qwen still has to decide what to compute, how to call the calculator, and how to use the result.

The author observed exactly this kind of failure: the CPU had already returned the correct answer, but Qwen reasoned again on its own and ended up with a wrong result, or got stuck in a loop of repeated tool calls.

So the CPU solves the problem of deterministic execution; it does not eliminate the probabilistic nature of the language model itself.

### Does It Affect the Original Q&A Ability?

This is another question worth looking at.

Qwenputer can still chat normally, explain code, answer knowledge questions, and do logical reasoning.

That's because the author kept the original Qwen3.5-4B weights, and the added compute circuitry also tries to avoid interfering with the language model during normal text generation.

MMLU results for the earlier CHIP-8 version:

| Model | MMLU accuracy |
|---|---:|
| Original Qwen3.5-4B | 71.7% |
| Qwenputer CHIP-8 | 71.9% |

The RISC-V version also went through text-behavior consistency tests, and its output distribution deviates only slightly from the original Qwen.

Current evidence suggests that adding the compute circuitry largely preserves the original language abilities, but it does not show any general improvement on tasks such as general logical reasoning or code understanding.

In other words, it is still a language model that can answer questions and reason normally; it simply gains an internal computing capability when exact calculation is needed.

## 6. Another Interesting Experiment: A File System Inside the Model

Beyond the CPU, the author also built a very interesting extension: a file system constructed inside the model.

Since Gated DeltaNet can already serve as RAM, structured data storage can be built on top of it.

In an experimental branch, the author added five kinds of operations:

```text
put("name", "Alice")
get("name")
append("notes", "New information")
list()
delete("name")
```

These operations are likewise executed by the compute circuitry inside the model, with no external database or file system service.

File names are hashed and mapped to directory locations in the Gated DeltaNet state, while file contents are stored in other state matrices.

The current experimental version supports up to 512 files, with a total capacity roughly equivalent to 53,000 tokens of text.

### What Does This Mean for Agent Memory?

Traditional agent memory systems usually rely on a separate storage service:

![Architecture of a traditional agent relying on an external memory service, database, and vector store](https://leafw-blog-pic.oss-cn-hangzhou.aliyuncs.com/qwenputer-agent-external-memory.png)

Qwenputer explores another possibility:

![Architecture of an agent's internal CPU using Gated DeltaNet memory to store key-values, file directories, and file contents](https://leafw-blog-pic.oss-cn-hangzhou.aliyuncs.com/qwenputer-gdn-memory-flow.png)

What's especially interesting is that this memory can persist across conversations.

Because file data is stored in Gated DeltaNet's state matrices, as long as that runtime state is saved and then restored in the next conversation, the previously saved files can be accessed again.

Note that the dynamic information is not written into the model parameters through retraining.

**The model weights provide the read/write capability; the runtime state holds the actual data.**

The author also designed cross-conversation memory tests.

On a set of fact-update questions, the Qwenputer file system version reached 90% accuracy, versus 30% for a baseline using past chat history as context. On another cross-session recall test, the file system version reached 83.3%, compared with 78.9% for a baseline equipped with an external Python memory tool.

The sample sizes are still limited, but the experiment shows that a model's internal recurrent state has the potential to serve as explicit memory.

Of course, this approach is still a long way from a real production-grade memory system.

Persistence, concurrency, transactions, permission isolation, and failure recovery are not automatically solved just by putting data into the model state.

Still, from a model-architecture perspective, it is a new direction worth studying.

## 7. What Are the Current Limitations?

Qwenputer is still an experimental project.

First, performance.

Advancing CPU instruction execution through token generation costs far more than an ordinary CPU. For real applications, calling external Python, Java, or native compute libraries is usually more efficient.

Second, model size.

Because of the added compute circuitry and a wider hidden dimension, the full model's BF16 checkpoint is about 18.8 GB, nearly twice the size of the original model. The author notes that a considerable portion of this is zero padding.

Third, runtime compatibility.

The current version needs the `RvChat` driver to load firmware, manage state, and isolate the CPU trace; it cannot yet work purely through a generic model inference pipeline.

Finally, the software ecosystem.

Although the underlying RISC-V CPU has already run C and MicroPython programs, MicroPython has mainly been tested on the standalone compute core and has not yet been fully integrated into the merged chat model.

The author's next plan is to let Qwen generate Python code directly and then execute it via the embedded MicroPython.

So at this stage, Qwenputer has proven the feasibility of executing CPU instructions inside a neural network, but it cannot yet be regarded as a general-purpose in-model code execution environment.

## 8. What I Think Qwenputer Really Means

After reading the article, I think the most noteworthy thing is not actually the result that "Qwen can run a CPU internally."

The CPU is a very intuitive proof of concept; the three directions behind it may be of greater research value.

### 1. Neural Network Weights Can Carry Compiled Programs

The capabilities of traditional large models come mainly from training.

We use data to teach models language, knowledge, logic, and code.

Qwenputer demonstrates another way to give a model capabilities: designing neural network weights directly with a compiler so that they perform specific deterministic functions.

For example, giving a model explicitly designed arithmetic circuits, data validation circuits, or parsers for specific formats.

These functions don't necessarily require retraining the whole model.

From this angle, future models may contain both learned capabilities and compiler-generated deterministic modules.

### 2. A Model's Internal State Space May Take On More Responsibilities

Gated DeltaNet was originally used to maintain the recurrent state of a language model as it processes context.

Qwenputer shows that, with suitably designed weights, these states can act as precise, addressable storage.

This offers some inspiration for future model-native memory.

Some state could handle language understanding, some could handle structured data storage, and there might even be dedicated state for executing deterministic programs.

Of course, we can't yet conclude that this kind of architecture will replace databases or external memory services, but it at least proves that such capabilities can be implemented inside a neural network.

### 3. Deterministic Computation Can Go Deep Inside the Model

Most agent architectures today separate the model from its tools.

The LLM handles understanding and decision-making, while external programs do the actual execution.

This architecture is mature and flexible, and better suited to most engineering scenarios today.

Qwenputer instead tries to make certain deterministic execution capabilities part of the model's own computation.

Building on this, the author also investigated two questions:

First, whether a model can store reasoning information in its RNN state and thereby bypass traditional chain-of-thought monitoring.

Second, whether monitoring logic can be compiled into the model weights to create an internal monitoring mechanism that the model itself cannot easily switch off.

Both directions suggest that precise control over a model's internal state and computation paths may have research value far beyond arithmetic.

## Final Thoughts

From a practical engineering standpoint, Qwenputer currently has no clear advantage in performance, size, or runtime complexity.

Having the model call a Python tool is obviously far more efficient than executing thousands of RISC-V instructions inside a neural network.

But the significance of this research is that it demonstrates a possibility that few had ever actually realized:

**A neural network can learn language and reasoning through training, and it can also, through directly constructed weights, have deterministic computing circuits and programmable state storage.**

From basic logic gates, to adders, registers, and RAM, all the way to a complete RISC-V CPU and an experimental file system, the author is really exploring the feasibility of mapping traditional computer architecture into a neural network.

In my view, Qwenputer's two most noteworthy achievements are constructing Gated DeltaNet into precisely addressable RAM, and using a compiler to directly generate model weights that carry executable logic.

Whether this eventually develops into more practical computing and memory architectures will require further research.

But at least this time, the author has made a large language model that can chat normally run a virtual CPU that genuinely follows RISC-V instruction semantics, inside its own neural network.

## References

1. [Divyansh Agrawal, Qwenputer: a fully functioning, deterministic RISC-V CPU inside Qwen3.5](https://divagr.com/blog/qwenputer)
2. [GitHub: divagr18/qwenputer](https://github.com/divagr18/qwenputer)
3. [RV32 inside Qwen3.5: technical design and experiment notes](https://github.com/divagr18/qwenputer/blob/main/experimental/riscv/docs/rv32.md)